Rainbow Runner studio and DVD addon internals

Reverse engineering is fun !

Rainbow Runner G-series (RRG)

This is what I found out when I tested the cards internal connections:

Have a look at the following pictures:

Overview of the Rainbow Runner card
Showing A2 (the green one) which connects the JPEG codec control signals with the connector besides. Above you find A13, responsible for routing RD and WR to the JPEG codec.
Showing the main chips on the card. A8 assists the Samsung KS0127 with logic functions. A14 routes the KS0127' graphics output to the framebuffer interface C2.

Zoran connections

JIRQ connects to C2 (the "bigger" main connector), it's the upper third pin from the left.
START connects to Q2 (Pin 11) on A2. (see also info on A2).
SLEEP connects to Q1 (Pin 6) on A2.
RESET connects to Q0 (Pin 2) on A2.

Samsung connections

The Samsung KS0127 video decoder is responsible for taking the video input from the connectors and the TV tuner, and converting it into a digital video format that can be read by the MGA G200 chip. It is already working quite well, therefore it is not needed to examine it more thouroughly.

Several pins on C2 transmit the graphics information from the Samsung video decoder. If needed, I can post the exact pin assignment.
Pin PORTA goes to A8, which in its turn enables the routing of the graphics information from the video decoder (Y0-Y7) to the frame buffer connector C2.

A2:s functions

Please remember that I am not completely sure if A2 is a Quad D-type flip flop !. But this assumption seems quite plausible, if you look at the pins connections and (assumed) functions.
Get Philips' documentation about a 74LV125. (This chip is also used on the DVD module, it is called A4 there).

D0 (4) -> C1, Pin 26
D1 (5) -> C1, 25
D2 (12) -> C1, 7
D3 (13) -> C1, 5
CP (Clock, 9) -> C1, 18
!MR (Master Reset, 1) -> C1, 10
Q0 (2) -> Zoran !RESET
!Q1 (6) -> Zoran !SLEEP
!Q2 (11) -> Zoran !START
!Q0, Q1, Q2, Q3, !Q3: Not connected

This is why I assume A2 to be very important in communicating with the Zoran JPEG codec. To control the different lines, one would have to prepare the data att the Dx pins, and run a clock pulse to CP (and of course deactivate the master reset line)...
Update: The things said above are true, but the MGA G200 is controlling the Clock and Master Reset on its own. One "just" has to play around with the MISCCTL register in the MGA G200, and it does the rest ... just a pity that we don't know the exact assignments, but at least some are known for sure:

Databit 2 connects to ZR36060 RESET
Databit 3 connects to ZR36060 SLEEP

So Db 2 corresponds to C1, 26 and Db 3 corresponds to C1, 25 ? Interesting - then let's extrapolate that to Db 0 <=> C1, 24 and Db 1 <=> C1, 23 ....

Ah, how strange, this is exactly where the DVD addon's RESET and STANDBY controls sit ! Ha, I like logic design ;) ;) ... See below for a table on the assumed functions of the MISCCTL register in the MGA G200 ...

C1

My numbering of C1, the "smaller" main connector, is the following:

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

15 14 13 12 11 10  9  8  7  6  5  4  3  2  1

Where pin 1 is the "non-existing" pin.

C2

The "bigger main connector is numbered as:

12 11 10  9  8  7  6  5  4  3  2  1

13 14 15 16 17 18 19 20 21 22 23 24

This is the frame buffer interface - I presume it is quite similar to a standard VGA feature connector ... the upper, third pin from the left (to the right above the "dead" one) is the Zoran !JIRQ. The lower pins in the middle transmit the graphics information.

The A13 chip

It seems to act as a read-write enable chip for the Zoran, doesn't seem very important, as we are already able to talk to the Zoran, anyways. I assume it to be a standard 74LV125, you can get the docs from e.g. Philips.

1x: not connected ?
2A(5) -> C1, 28
2Y(6) -> ZR36060 !RD
2!OE(4) -> C1, 19
3A(9) -> C1, 3
3Y(8) -> ZR36060 !WR
3!OE(10) -> C1,19
4x: not connected.

The other small chips

The other chips haven't been identified yet.

The A8 chip

Unfortunately I wasn't able to find all it's connections. Once again, I assume it to be a standard 74LV125, you can get the docs from e.g. Philips.

1A(2) -> ?
1Y(3) -> C2,17
1!OE(1) -> A14-1!G
2A(5) -> C2,17
2Y(6) -> ?
2!OE(4) -> KS0127 ,PORTA
3A(9) -> ?
3Y(8) -> A14-1!G
3!OE(10) -> KS0127 , PORTA
4x: not connected ?

A14 - video router

This chip seems to route the video information from the video decoder to the frame buffer, assuming that it is a standard 74LS244 octal non-inverting buffer/line driver with 3-State outputs.

1 !G (1) and 2 !G (19) are combined, and connected to A8 - 1!OE and A8-3Y (which seems to be the input).
All input pins (1A1 - 2A4) are connected to Y0 - Y7 on the Samsung video decoder KS0127.
All output pins (1Y1 - 2Y4) are connected to the VGA feature connector (frame buffer connector) on C2.

A1 - the unknown one

I couldn't identify this chip yet, but I don't think it is important to make the driver work.

The DVD module

... was very interesting to examine, too :-) ... It seems to be the complement to the RRG, and it "fills" up the rest of the pins, which leads me to the assumption that these two cards were designed to work together on the same bus (which they actually do ;) ). It helped also in building a "generalized" concept of the card designs.
Before you continue, see the DVD addon module's homepage for in-deep information.

A4:s functions

Please remember that I am not completely sure if A4 is a Quad D-type flip flop !. But this assumption seems quite plausible, if you look at the pins connections and (assumed) functions.
Get Philips' documentation about a 74LV125.

See the similarities to the A2 chip on the RRG ? This strengthens my assumptions about the chip type and the card design.

D0 (Pin 4) -> C1, Pin 24
D1 (1) -> C1, 23
D2 (12) -> C1, 9
D3 (13) -> C1, 2 & C1, 4 (strange ? NC, anyways)
CP (Clock, 9) -> C1, 18 (deja vu !)
!MR (Master Reset, 1) -> C1, 10 (same here !)
Q0 (2) -> Zoran RESET
Q1 (7) -> Zoran STANDBY
!Q2 (11) -> Zoran !HCS (or "HCS#", Host Chip Select)
!Q0, !Q1, Q2, Q3, !Q3: Not connected

(If you want to verify these connections on your card, bear in mind that the C1 connector is "reversed" (pinout horizontally flipped) on the DVD module !)

Thoughts about the MISCCTL register on the MGA G200

Now that I have reverse-engineered the different control lines on the cards, and Mike sent me the information about controlling the ZR36060 RESET and SLEEP line with the MISCCTL register, I will do some wild speculating about the bit positions of the other control lines:

Databit Nr.	Pin on C1 connector	Connected to
0	24	DVD ZR36700 RESET
1	23	DVD ZR36700 STANDBY
2	26	RRG ZR36060 RESET
3	25	RRG ZR36060 !SLEEP
4	7	RRG ZR36060 !START
5	9	DVD ZR36700 HCS#
6	4	Not connected
7	5	Not connected

Except for Databit nr. 2 and 3, all other positions are just guesses, and can be completely different !.

Some basic assumptions here:

Each control pin (and hence, its corresponding bit in MISCCTL) has its own control line, and the DVD and RRG do not share any control bits.
Looking at the pin layout, one could assume that the bit assignment is at least right for the nibble (3 bit) group it is in (which means, that Databit Nr.4 , for example, maybe has pos. 5, 6 or 7, but not 0, 1, 2 or 3).

You are welcome to mail me for any more questions.

Gernot Ziegler
gz@lysator.liu.se
Page last modified: Feb 1, 2000